Senior Digital IC Design Engineer

  • Core Technology
  • Enschede, Netherlands

Senior Digital IC Design Engineer

Job description

The objective of the senior Digital IC Design Engineer is to contribute as a team member of the mCube IC design team, primarily for the creation of Motion Sensor MEMS (Micro-Electro-Mechanical System) IC’s manufactured in monolithic CMOS by TSMC. The IC design team is currently located in San José California, a second design site is being established in the office of Xsens Enschede, a subsidiary of mCube Inc., a leader in monolithic MEMS IC’s for motion capturing (www.mcubemems.com). Reporting line will be functionally into the Digital Design Manager, Tony Maraldo at mCube HQ, locally into the team leader of the IC Design team.

Requirements

  • The ideal candidate must have:
    • A (deep) understanding of
      • Verilog HDL, RTL design, verification
      • Test bench, vector, and verification suite construction, automated design validation and regression.
      • Lab/validation experience with prototype designs, ASIC and FPGA.
    • Experience in:
      • taking a product from specification, to design, verification and release for high-volume production
      • ECO design flow and releases
      • Digital signal processing - filter design, etc.
    • Highly skilled in timing-simulations, static timing analysis, and closure.
    • Knowledge of Cadence simulation tools and Encounter/VDI synthesis flow
    • Excellent communication skills, verbal and written.

The ideal candidate must have:

  • A (deep) understanding of
    • Verilog HDL, RTL design, verification
    • Test bench, vector, and verification suite construction, automated design validation and regression.
    • Lab/validation experience with prototype designs, ASIC and FPGA.
  • Experience in:
    • taking a product from specification, to design, verification and release for high-volume production
    • ECO design flow and releases
    • Digital signal processing - filter design, etc.
  • Highly skilled in timing-simulations, static timing analysis, and closure.
  • Knowledge of Cadence simulation tools and Encounter/VDI synthesis flow
  • Excellent communication skills, verbal and written.

Desirable:

  • Experience with System Verilog or UVM.
  • Microcontroller firmware development, ARM/MIPS architecture or equivalent.
  • Floor-planning and physical implementation experience, LEF/DEF/block handoff to layout team.
  • Use of Xilinx FPGA design tools.
  • Familiarity with Matlab, C, Perl, TCL or Python.


Compensation

The compensation package will include a base salary benchmarked in the Enschede area at median+ level, include 8% holiday allowance, a profit-sharing bonus and additional conditions aligned with Xsens local benefits.